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 .., .., .. - // M.: , 2007, 220c. |
| .. // .: , 2011. 136 c. |
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 S. Gavrilov, A. Glebov, S. Rusakov, D. Blaauw, L. Jones, G. Vijayan. Fast Power loss calculation for digital static CMOS circuits // Proc. Of European Design and Test Conference (ED&TC), Paris, France, 1997, P.411. |
| S. Gavrilov, A. Glebov, S. Pullela, S. Moore, G. Vijayan, A. Dharchoundhury, R. Panda, D. Blaauw. Library-less synthesis for static CMOS combinational logic circuits // Proc. of IEEE/ACM intern. Conference on computer aided design (ICCAD), San Jose, CA, 1997, P.658. |
| A. Glebov, S. Gavrilov, D. Blaauw, S .Sirichotiyakul, C. Oh, V. Zolotov. False-Noise Analysis using Logic Implications // Proc. of IEEE/ACM intern. Conference on computer aided design (ICCAD), San Jose, CA, 2001, P.515. |
| A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, C. Oh. False-Noise Analysis Using Resolution Method // Intern. Symp. on Quality Electronic Design (ISQED), San Jose, CA, 2002, P.437. |
A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov. False-noise analysis using logic implications // ACM Transactions on Design Automation of Electronic Systems (TODAES), 2002, v.7, 3, P.474-498. 
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| .. , .. , .. . // , , 2002, 5, C.60. |
| .. , .. , .. . // , 2002, 6, C.40. |
| .. , .. , .. . // , 2002, 4., C.40-47 |
| D.Blaauw,S.Gavrilov,A.Glebov,Y.Egorov,D.Nadezchin,etc. SOI transistor model for fast transient simulation // In Proc. of ICCAD, 2003, P.120-127.
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| S.Gavrilov, A.Glebov, V.Zolotov, etc. False-Noise Analysis for Domino Circuits // In Proc. of DATE, Paris Feb. 2004, P.784-789.
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| S.Gavrilov,A.Glebov,R.Soloviev,M.Becer,etc. Delay Noise Pessimism Reduction by Logic Correlations // In Proc. of ICCAD, 2004, P. 160-167. |
| .., ..,... // , , N6, 2004, C.64-72. |
| .., ..,... " // , 10, 2004, C.2-7. |
| .., .., ... , // , , 2005. - 6, . 61-67. |
| .., .., .. // . , 2006, 5, .99-106. |
| .., .., .. // , 2006, 12, .2-12. |
| .., .., .. // , , 2007, 2, .78-84. |
| .., .., .., .. // . . 2007. - 4. . 28-36. |
| Savithri Sundareswaran, Sergey Gavrilov, Roman Soloviev, Rajendran Panda A Timing Methodology Considering Within-Die Clock Skew Variations // IEEE International SOC conference, 2008, Newport Beach, CA, P.351-356.
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| .. , .. , .. - // . . 2008. 5. .41-50. |
| .., .., .. . // . . 2008. 6. .30-40. |
| .. , .. , .. // . 2009, 3, C.20-24. |
| .., .. , .. , .. // . 2009, 7, .3238 |
| Alexander Stempkovsky, Alexey Glebov, Sergey Gavrilov. Calculation of Stress Probability for NBTI-Aware Timing Analysis // Proc. of ISQED, 2009, P.714-718.
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| .., .., .. // . . 2010. 3. . 51-59. |
| .., .., .. // . . 2011. 7. .188-197. |
| S. V. Gavrilov, O. N. Gudkova and Yu. B. Egorov. Methods of accelerated characterization of VLSI cell libraries with prescribed accuracy control // Russian Microelectronics, Vol.40, N7, 2011, P.476-482. |
| .. , .. , .. . - . // . . 2012. - 4. C. 40-49 |
| .. , .. , .. . -. // . . 2012. - 7 (132). - . 70-76. |
| .. , .. , .. . - . // . . 2012. - 7 (132). - . 85-91. |
| S.V. Gavrilov, O.N. Gudkova, A.L. Stempkovskiy. The Analysis of the Performance of Nanometer IP-blocks Based on Interval Simulation. // Russian Microelectronics, Vol.42, N7, 2013, P. 396402. Pleiades Publishing, Ltd., 2013. |
| Sergey Gavrilov, Olga Gudkova, Roman Soloviev. Timing Analysis for Complex Digital Gates and Circuits Accounting for Transistor Degradation // Proceedings of SEUA. Series Information technologies, Electronics, Radio engineering. Issue 16, N1, 2013, P.84-93 |
| .., .., .. // . 2014. 6. . 5863. |
| .., .., .. - - // . 2014. 8. . 4450 |
| .., .., .. // . . 2014. 7, C. 66-75 |
| .., .., .. - - // . . 2014. 7, C. 58-66. |
| Sergey Gavrilov, Galina Ivanova, Pavel Volobuev, Aram Manukyan. Methods of logical synthesis for library elements and blocks with regular layout structure // 2015 IEEE 35th International Conference on Electronics and Nanotechnology (ELNANO-2015), 2015, P. 138-141. |
| .., .. // . 2015. 2 ( 52). . 56-64. |
| Gavrilov S., Ivanova G. Simultaneous Logic and Layout Synthesis for Fin-fet Based Elements with Regular Layout in olysilicon and Diffusion // Proceedings of IEEE East-West Design & Test Symposium (EWDTS2015), 2015, P. 264-267. |
| .., .. // . 2015. ( 53). . 29-35. |
| .., .., .., .. // . . 2015. 6(167). C. 255-262. |
| .., .., .., .. // . . 2015. 6(167). C. 106-115. |
| .., .., .., .., .. // . 2015, . 21, 11, . 821-826. |
| A.L. Stempkovsky, S.V. Gavrilov, I.V. Matyushkin, and G.S. Teplov. On the Issue of Application of Cellular Automata and Neural Networks Methods in VLSI Design) // Optical Memory and Neural Networks. 2016. Vol. 25. No. 2. Pp. 7278. |
| .., .. - // . . 2016. 6 (179). C. 131-141. |
| .., .., .. // . . 2017. . 22. 3. . 266-275. |
| S. V. Gavrilov, S. I. Gurov, T. D. Zhukova, V. S. Rukhlov, D. I. Ryzhova, and D. V. Telpukhov. Methods to Increase Fault Tolerance of Combinational Integrated Microcircuits by Redundancy Coding // Computational Mathematics and Modeling, 2017, Vol. 28, No. 3. Pp. 400 406. |
| Gavrilov S.V., Matyushkin I.V, Stempkovsky A.L. Computability via Cellular Automata // Scientific and Technical Information Processing. 2017. V.44, 5, Pp. 1-15. |
| .., .., .. // 2018610141 09.01.2018. |
| .., .., .A., .., .., .., // , 2019, 48, 3, C. 211223. DOI:10.1134/s0544126919030050 |
| Gavrilov S.V., Zheleznikov D.A., Zapletina M.A., Khvatov V.M., Chochaev R.Z., Enns V.I. Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip // Russian Microelectronics. 2019. 48(3), P. 176-186. DOI:10.1134/s1063739719030053 |
| Khvatov V.M., Zheleznikov D.A., Garbulina T.V., Gavrilov S.V. Post-Route Performance Estimation Method for Reconfigurable System-on-a-Chip // 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Moscow, 2020, pp. 1804-1808. DOI: 10.1109/EIConRus49466.2020.9039262 |
| .., .A., .., ., .. // . . 2020. . 25. 5. . 410422. DOI: 10.24151/1561-5405-2020-25-5-410-422 |
| Enns V.I, Gavrilov S.V., Zapletina M.A. Set Based Theoretical Approach to the Representation of Routing Stage in the Design Flow for the Heterogeneous FPGAs and Reconfigurable SoCs // Russian Microelectronics, 2021, Vol. 50, No. 6, pp. 463-470. DOI: 10.1134/S1063739722010061 |
| 352. Zapletina M.A., Gavrilov S.V. Pathfinder Algorithm Modification for the FPGA Interconnect Routing Stage // Russian Microelectronics Vol. 51, No.7, 2022 |
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